MCP Tools DirectoryAbout this integration
AI-agent MCP server for FPGA design: compile, validate & generate Verilog from C⏚ HDL.
- Transport
- stdio
- Authentication
- none
- Initial setup
- unknown
- Runtime
- unattended
- Evidence
- documented
- Version
- 0.2.1
- Package
- cg-agent-kit
- Last compatibility test
- Not independently tested
Connect your agent
cg-agent-kitThe open compiler JAR is not bundled by the documented installation and must be obtained or built separately. Some simulation functionality is commercial; the documented Icarus Verilog backend is open. Package and local toolchain behavior were not executed or independently security-audited.
Capabilities: Compile and validate C⏚ hardware descriptions, Generate synthesizable Verilog, Run supported simulation backends, Synthesize with Yosys, Return bundled examples and language documentation
Connected profiles
Additional details
io.neosyn/cg-agent-kit
Source ↗ · Checked 2026-09-170.2.1
Source ↗ · Checked 2026-09-17CC0-1.0; package licenses are separate
Source ↗ · Checked 2026-09-17pypi
Source ↗ · Checked 2026-09-17cg-agent-kit
Source ↗ · Checked 2026-09-190.2.1
Source ↗ · Checked 2026-09-19The publisher documents cg-mcp-server as a persistent stdio MCP command for desktop and editor clients. The package was not executed in this review.
Source ↗ · Checked 2026-09-19No remote account credential is documented for the open toolchain. A separately obtained or locally built C⏚ compiler JAR is a required file prerequisite; optional Yosys and Icarus Verilog tools enable additional functions.
Source ↗ · Checked 2026-09-19The MCP client launches cg-mcp-server over stdio and passes CG_JAR as the local compiler-JAR path.
Source ↗ · Checked 2026-09-19Publisher documentation reviewed; package and integration endpoint not executed or independently security-audited.
Source ↗ · Checked 2026-09-19